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A systolic architecture for computing inverses and divisions in finite fields GF(2m)

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2 Author(s)
Chin-Liang Wang ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Jung-Lung Lin

A new serial-in serial-out systolic array is presented for performing the element inversion in GF(2m) with the standard basis representation. The architecture is highly regular, modular, nearest neighbor connected, and thus well suited to VLSI implementation, It has a latency of 7m-3 clock cycles and a throughput rate of one result per 2m)-1 clock cycles. This speed performance is much better than those of the previous implementations. Without change in hardware design, the proposed inversion array can be directly used for computing the division in GF(2m)

Published in:

Computers, IEEE Transactions on  (Volume:42 ,  Issue: 9 )

Date of Publication:

Sep 1993

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