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ILLIADS: a fast timing and reliability simulator for digital MOS circuits

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3 Author(s)
Y. -H. Shih ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; Y. Leblebici ; S. -M. Kang

The authors introduce ILLIADS as a fast MOS timing and reliability simulator for very large digital MOS circuits. The use of the proposed general circuit primitive not only provides better accuracy but also significantly reduces the simulation time. The use of an analytic solution embedded in the simulation engine improves both the simulation speed and the accuracy. Postponing the waveform approximation process provides better waveform approximation even for non-fully-switching waveforms and glitches. The channel length modulation effect is captured accurately in fast timing simulation with only 10% of speedup tradeoff. It is also shown that ILLIADS manifests the charge sharing problem. The modified PWCTC algorithm, PWCTC-W, which handles circuits with feedback, is introduced and shown to be superior to the dynamic-windowing scheme. It also does not manifest the window-growing problem and is insensitive to the level of strongly concerned component (SCC) hierarchy. The use of this algorithm keeps the speedup of ILLIADS over SPICE for circuits with feedbacks at the same level as that for combinational circuits

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:12 ,  Issue: 9 )