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Restructuring of square processor arrays by built-in self-repair circuit

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2 Author(s)
P. Mazumder ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; Y. -S. Jih

The authors introduce two types of neural networks that can be integrated into array-type very-large-scale integration/wafer-scale integration (VLSI/WSI) chips, allowing them to restructure themselves automatically so that, in the presence of multiple random faults, the array circuits can perform their computations correctly. In the first implementation, the neural network is interconnected and programmed so that it can execute a maximum matching algorithm and thereby substitute appropriate fault-free spare elements for the faulty components. The second implementation rearranges the surviving fault-free processors to restore the logical structure, and it can adjust its interconnection complexity based on the quality of solution (i.e., performance) desired. These two approaches are compared with the traditional reconfiguration algorithms, and by simulation it is shown that the neural network techniques provide superior performance (i.e., higher survivability rates). It is also shown that the intrinsic fault-tolerant nature of neural networks provides a degradable reconfiguration control even in the presence of faulty neural network components

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:12 ,  Issue: 9 )