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Characterization and high-speed digital application of GaAs MESFETs on substrates

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5 Author(s)
Onozawa, S. ; Oki ELectr. Ind. Co. Ltd., Tokyo ; Yamamoto, N. ; Kimura, T. ; Sano, Y.
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Summary form only given. The authors optimized the device structure to suppress the short channel effect due to the residual stress in GaAs/Si substrates and improved the microscopic uniformity. The residual-stress problem was solved by introducing a p-layer (C+ : 140 keV) buried under the n-type channel (Si+: 20 keV) in the n+ self-alignment technique with refractory W-Al gate. The authors then evaluated the microscopic uniformity of the device on GaAs/Si using 60-μm×60-μm-pitch FET arrays, and found that it is improved by introducing the p-layer. To evaluate the dynamic characteristics, a direct-coupled FET logic (DCFL) ring oscillator was fabricated using a 0.3-μm-gate MESFET on the GaAs/Si substrate. The propagation delay was as small as 19.9 ps/gate at a supply voltage of 2 V

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Electron Devices, IEEE Transactions on  (Volume:40 ,  Issue: 11 )