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A high speed and low power on CMOS/SOI technology

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3 Author(s)
Lee, M. ; Dept. of Electron Eng., Tokyo Univ. ; Fujishima, M. ; Asada, K.

Summary form only given. The propagation delay times were improved up to two times in deep-submicron CMOS/SIMOX ring oscillators by reducing the poly-Si gate thickness (tm). The measured power dissipations with 0.1- to 0.25-μm gate length are under 1.5 fJ, while theoretical minimum power dissipations can be reduced down to 0.1 fJ for 0.15-μm gate length at a supply voltage of 1.5 V. SOI technology shows promise for high speed and low power by reducing the gate fringing capacitance which is correlated to tm

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Electron Devices, IEEE Transactions on  (Volume:40 ,  Issue: 11 )