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A design verification method for programmable controller software

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5 Author(s)
M. Takamoto ; Hitachi Ltd., Ibaraki, Japan ; Y. Kobayashi ; N. Yamada ; T. Nakamura
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The conditions under which sequentialized logic in software exhibits undesirable behavior are explored and a design verification method is proposed. The method consists of two steps. (1) Input signals to the extracted section of the sequential control diagram including a feedback loop, which cause three kinds of potential states, (a) reset failure, (b) set failure, and (c) simple delay, are applied to the feedback loop in order to evaluate a failure possibility. (2) The input signals that cause a failure of the circuit output are identified using a simulation technique of backward signal propagation. Experiments with a simple sequential circuit confirms that this method can detect all the conditions which lead to undesirable behavior

Published in:

Industrial Electronics, Control and Instrumentation, 1991. Proceedings. IECON '91., 1991 International Conference on

Date of Conference:

28 Oct-1 Nov 1991