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Computer based wafer inspection system

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2 Author(s)
Mital, D.P. ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore ; Teoh, E.K.

Aiming at the support of automated testing of semiconductor production, an automatic wafer pattern inspection system has been developed. The proposed system is capable of detecting defective patterns with a size of about 1-5 μm. The testing speed is much faster than that of a human operator. The false alarm rate is also very low. This performance is achieved by the use of a knowledge-based method utilizing design pattern data. Rule-based decisions are used to identify optimum parameters for inspection and possible defects. The main use of the design pattern data is to specify the inspection area, to designate optimum parameters for inspection, and to identify classification of the defects. Because of the limitations of lab facilities, the system has been tested on simple wafers. The results have been very encouraging. The proposed approach was found to be superior to other techniques used for automatic visual inspection because it frees one from the precise alignment needed to compare images

Published in:

Industrial Electronics, Control and Instrumentation, 1991. Proceedings. IECON '91., 1991 International Conference on

Date of Conference:

28 Oct-1 Nov 1991

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