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Reconfiguration and analysis of a fault-tolerant circular butterfly parallel system

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1 Author(s)
N. -F. Tzeng ; Center for Advanced Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

The butterfly parallel system has a regular and simple interconnection pattern, making it suitable for VLSI or WSI implementation. The authors propose an effective fault-tolerant technique for the circular butterfly parallel system to ensure its rigid full butterfly structure even in the presence of failures, addressing reconfiguration in detail. The resulting butterfly system has L levels, involves (1/log2 L)% spare processing elements (PEs), and approximately 50% additional links. The reconfiguration process of the design in response to any operational fault is easy and can be performed in a distributed manner. The reliability and layout of this proposed design are evaluated analytically. This design, due to its specific configuration, exhibits significant improvement in reliability while taking only moderately more layout area

Published in:

IEEE Transactions on Parallel and Distributed Systems  (Volume:4 ,  Issue: 8 )