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Hierarchical design space exploration for a class of digital systems

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2 Author(s)
Sreenivasa Rao, D. ; Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA ; Kurdahi, F.J.

This paper presents an architectural synthesis approach for a widely used class of digital systems characterized by inherent regularity in their description. This approach relies on a novel modeling or abstraction of the problem domain to facilitate a hierarchical solution method. The modeling is based on exploiting the inherent regularity in the system description to cluster its behavioral operations. The method emphasizes prudent postponement of design decisions until enough physical design information is available to estimate layout effects like wiring; we use well-known area-delay estimators for this purpose. The approach has the advantage that it keeps track of a set of potentially good candidate solutions, rather than narrowing down to a single solution very early in the design process. Through an extensive set of experiments on well-known DSP design examples, we demonstrate the advantages that such distinctive features have to offer; the impact of hierarchy on several important issues, such as interconnection area, extent of design space explored, etc., is presented.<>

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:1 ,  Issue: 3 )