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Synthesis of timed asynchronous circuits

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2 Author(s)
Myers, C.J. ; Dept. of Electr. Eng., Stanford Univ., CA, USA ; Meng, Teresa H.‐Y.

The authors present a systematic procedure for synthesizing timed asynchronous circuits using timing constraints dictated by system integration, thereby facilitating natural interaction between synchronous and asynchronous circuits. Their timed circuits also tend to be more efficient, in both speed and area, compared with traditional asynchronous circuits. The synthesis procedure begins with a cyclic graph specification to which timing constraints can be added. First, the cyclic graph is unfolded into an infinite acyclic graph. Then, an analysis of two finite subgraphs of the infinite acyclic graph detects and removes redundancy in the original specification based on the given timing constraints. From this reduced specification, an implementation that is guaranteed to function correctly under the timing constraints is systematically synthesized. With practical circuit examples, it is demonstrated that the resulting timed implementation is significantly reduced in complexity compared with implementations previously derived using other methodologies.<>

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:1 ,  Issue: 2 )