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M*N Booth encoded multiplier generator using optimized Wallace trees

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1 Author(s)
J. Fadavi-Ardekani ; AT&T Bell Lab., Allentown, PA, USA

The architecture of a design method for an M-bit by N-bit Booth encoded parallel multiplier generator are discussed. An algorithm for reducing the delay inside the branches of the Wallace tree section is explained. The final step of adding two N+or-M-1-bit numbers is done by an optimal carry select adder stage. The algorithm for optimal partitioning of the N+or-M-1-bit adder is also presented.<>

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:1 ,  Issue: 2 )