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MARVLE: a VLSI chip for data compression using tree-based codes

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4 Author(s)
Mukherjee, A. ; Dept. of Comput. Sci., Univ. of Central Florida, Orlando, FL, USA ; Ranganathan, N. ; Flieder, J. ; Acharya, T.

Describes the architecture and design of a CMOS VLSI chip for data compression and decompression using tree-based codes. The chip, called MARVLE, implements a memory-based architecture for variable length encoding and decoding based on tree-based codes. The architecture is based on an efficient scheme of mapping the tree representing any binary code onto a memory device. A prototype 2-mm CMOS VLSI chip has been designed, verified, and fabricated by the MOSIS facility. The chip has a 512*12 static RAM with an access time of 4 ns and logic circuitry for compression as well as decompression. The chip occupies a silicon area of 6.8 mm*6.9 mm and consists of 49695 transistors. The prototype chip yields a compression rate of 95.2 Mb/s and a decompression rate of 60.6 Mb/s with a clock rate of 83.3 MHz. The VLSI hardware can be used to implement the JPEG baseline compression scheme.<>

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:1 ,  Issue: 2 )