Referenced Items are not available for this document.
A multi-input Muller C-element has frequently been used for joining signal transitions or completion time detection in self-timed circuits. An n-input Muller C-element design which uses the multilevel logic design technique and has a symmetric format for any integer n >or=2 is presented. In comparison with series-parallel MOS structure implementations and C-element tree implementations, the present design has fewer restrictions in terms of n, less path delay, less delay variance from inputs to output, and less area consumption. Experimental validation based on an industrial standard cell library is presented.<
Published in:
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
(Volume:1
,
Issue:
2
)
Date of Publication: June 1993
- Page(s):
- 215 - 219
- ISSN :
- 1063-8210
- INSPEC Accession Number:
- 4508064
- Digital Object Identifier :
- 10.1109/92.238414
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- June 1993
- Sponsored by :
- IEEE Circuits and Systems Society
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