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Reliable and fast reconfigurable hierarchical interconnection networks for linear WSI arrays

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3 Author(s)
Sul, C. ; Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada ; McLeod, R.D. ; Pedrycz, W.

A self-pruning binary tree (SPBT) interconnection network architecture that tolerate faults in a wafer scale integration (WSI) environment is proposed. The goal of the SPBT network is to provide a reliable and a quickly reconfigured interconnection network architecture for linear WSI arrays. The proposed architecture uses a bottom-up approach to reconfigure a linear pipelined array on a potentially defective WSI array using a binary tree interconnection scheme. The binary tree is generated by successive formation of hierarchical modules. For N processing elements (PEs) on the wafer, reconfiguration time is O(log N). The propagation delay is bounded by Theta (log N) and is independent of the number of faulty PEs. Faults in the switching network as well as faulty processing elements are tolerated.<>

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:1 ,  Issue: 2 )

Date of Publication:

June 1993

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