By Topic

Hierarchical test pattern generation: a cost model and implementation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Min, H.B. ; Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA ; Luh, H.-t.A. ; Rogers, W.A.

A cost model for and implementation of a hierarchical test generation technique are presented. The cost model is based on fundamental test generation activities such as implication, justification, and backtracking. The model shows that the cost of hierarchical test generation grows as G log G under some realistic assumptions, while the cost of gate-level test generation may grow as fast as G2, where G is the number of gates in a circuit under test. This implies that hierarchical test generators should be much faster than flat test generators on large circuits. The implementation of the hierarchical test generation is fan-out-oriented and uses a minimal hierarchical representation of the circuit and functional level heuristics to perform implication, propagation, and backtracing with high-level functional models. Experiments with three hierarchically described circuits show that hierarchical test generation is 1.5 to 8.9 faster than flat gate-level generation

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:12 ,  Issue: 7 )