The authors evaluate the features of a gallium-arsenide E/D MESFET process in which a 32-b RISC microprocessor was implemented. The design methodology and architecture of this prototype CPU are described. The performance sensitivities of the microprocessor and other large circuit blocks to different process parameters are analyzed, and recommendations for future process features, circuit approaches, and layout styles are made. These recommendations are reflected in the design of a second microprocessor using a more advanced process that achieves much higher density and performance
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:28
,
Issue:
10
)
Date of Publication: Oct 1993