By Topic

A half-micron CMOS technology using ultra-thin silicon on insulator

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
P. H. Woerlee ; Philips Res. Lab., Eindhoven, Netherlands ; C. Juffermans ; H. Lifka ; W. Manders
more authors

A 0.5 mu m CMOS technology on ultra-thin film SIMOX SOI (silicon on insulator) material is described. The technology, material quality, and device properties are discussed. The impact of TiSi/sub 2/ salicidation on the NMOS device breakdown, self-heating, and anomalous hot carrier degradation of NMOS devices is discussed in detail. Furthermore, the successful fabrication of a large circuit with 70000 transistors using a 0.5 mu m technology on ultra-thin SOI material is presented.<>

Published in:

Electron Devices Meeting, 1990. IEDM '90. Technical Digest., International

Date of Conference:

9-12 Dec. 1990