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Mapping applications onto a cache coherent multiprocessor

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2 Author(s)
Nanda, A.K. ; Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA ; Bhuyan, L.N.

The authors present a technique to compute the communication times of programs on cache coherent distributed shared memory systems. Simulated annealing is used to obtain near-optimal mappings of program tasks onto processors. Various cost parameters are explored for determining efficient mappings of the program tasks onto the processors in the presence of cache coherence protocols. The techniques were demonstrated using the Sequent Balance multiprocessor and the Jacobi iteration problem. Measurement results confirm that the estimate of communication time is fairly accurate. The importance of accurate estimation of communication time for efficient mapping of program tasks in the presence of the cache coherence protocol was verified using measurements on the Balance multiprocessor

Published in:

Supercomputing '92., Proceedings

Date of Conference:

16-20 Nov 1992