By Topic

A case for wafer-scale interconnected memory arrays

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Tzi-cker Chiueh ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

The author describes a novel memory architecture, wafer-scale interconnected memory array (WIMA), that is intended to replace ultradensity monolithic DRAM (dynamic random access memory) ICs. This architecture employs the high-performance high-density interconnects provided by the multichip module technology, cache-embedding, and prime-degree interleaving to expose the internal parallelism not exploited by monolithic DRAMs. Using WIMA modules as the basic building blocks, a high-bandwidth, low-latency, and low-cost main memory system is proposed that could support the parallelism among multiple vector access streams. A novel indexing mechanism for prime-degree interleaving is developed which delivers fast and predictable memory access latency with modest hardware requirements

Published in:

Supercomputing '92., Proceedings

Date of Conference:

16-20 Nov 1992