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Sparse matrix computations: implications for cache designs

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1 Author(s)
Taylor, V.E. ; EECS Dept., Northwestern Univ., Evanston, IL, USA

High-performance cache designs are studied for the class of sparse matrix computations, which are often excluded from the general programs used in previous cache studies. In particular, the data that should be stored in the cache are identified, and the cache organization is studied in terms of associativity, size, write operation, write policy, block size, and number of read and write ports. Simulation results demonstrate that a 1-kword or 8-kbyte (one word is equal to 64 b), direct-mapped cache produces good results with almost all of the misses occurring from first time accesses. This cache size can easily fit on a chip, with plenty of room to spare for other components

Published in:

Supercomputing '92., Proceedings

Date of Conference:

16-20 Nov 1992