By Topic

Effect of data access delays and system partitionability on the dynamic performance of a shared memory multiprocessor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
S. Abraham ; Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA ; K. Padmanabhan

Any architectural or operational inefficiencies in multiprocessors with thousands of processors are likely to have a significant negative impact on the performance of the system. The authors examine two such issues in large-scale shared memory multiprocessors-the delays involved in accessing global shared memory, and the low processor utilization resulting from inefficient partitioning of the system among several tasks. These studies are undertaken using a simulation model that directly integrates the nondeterministic interconnection network delays encountered during shared memory accesses into the execution of tasks on processors. The results show the quantitative impact of interconnection network delay on system performance and point to ways of reducing this impact. Furthermore, when incoming tasks have large processor requirements, the system's inability to partition the processors among several tasks efficiently has a significant detrimental effect on performance. The effectiveness of some techniques to solve this partitionability problem is discussed

Published in:

Supercomputing '92., Proceedings

Date of Conference:

16-20 Nov 1992