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An efficient scaling procedure for domain CMOS logic

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1 Author(s)
Wurtz, L.T. ; Dept. of Electr. Eng., Alabama Univ., Tuscaloosa, AL, USA

The layout area required by a domino CMOS gate to support a specific response-time performance for a particular capacitive load can be substantially reduced by scaling the NFET chain. A scaling procedure that requires little execution time is described and illustrated by its application to AND, AOI, and OAI domino CMOS gates. The procedure is equally applicable to other forms of dynamics logic

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:28 ,  Issue: 9 )