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An STS-N byte-interleaving multiplexer/scrambler and demultiplexer/descrambler architecture and its experimental OC-48 implementation

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5 Author(s)

The authors present a byte-interleaving architecture for generating higher-order signals in the synchronous optical network (SONET) digital hierarchy and report on the implementation and system performance results of an experimental 2.488 Gbit/s SONET STS-3c to STS-48 (OC-48) byte multiplexer/scrambler and STS-48 (OC-48) to STS-3c byte demultiplexer/descrambler. The proper operation of the byte multiplexer and demultiplexer has been verified in an OC-48 experiment with a bit error rate (BER) of less than 10-14. It is shown that the byte-interleaving architecture leads to a simple and modular implementation of higher-rate interfaces (such as OC-192 at 9.95 Gbit/s) using state-of-the-art technologies

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Networking, IEEE/ACM Transactions on  (Volume:1 ,  Issue: 3 )