By Topic

Bonded wafer substrates for integrated detector arrays

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
J. J. Wang ; Adv. Res. & Applications Corp., Sunnyvale, CA, USA ; E. E. King ; P. Leonov ; D. H. Huang
more authors

Bonded wafer substrates that are optimized for integrating high-energy-particle silicon detector arrays with their readout electronics have been fabricated. The detectors are processed in the handle wafer, which is a 300-μm-thick, high-resistivity, <111> silicon wafer. This wafer is bonded to a primary wafer using a low-temperature process that does not affect the detector material. The support electronics are processed in the remnant of the primary wafer, which is a submicron-thick <100> silicon film formed by a bond-and-etchback procedure. These two materials are isolated from each other by a radiation-hardened dielectric film. The integration process is based on a low-temperature, radiation-hardened VLSI CMOS process that is also shown not to seriously affect the detector material

Published in:

IEEE Transactions on Nuclear Science  (Volume:40 ,  Issue: 5 )