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Simulation and optimization of binary full-adder cells in rapid single flux quantum logic

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2 Author(s)
Martinet, S.S. ; Dept. of Electr. Eng., Rochester Univ., NY, USA ; Bocko, M.F.

The authors consider the design of a binary carry full-adder cell using the logic gates and buffers belonging to the rapid single-flux-quantum (RSFQ) logic family. They have taken advantage of the unique properties of RSFQ pulse logic to realize two designs: one using two logic gates and a toggle flip-flop in two stages of logic, the other using two logic gates in one stage of logic. They have determined the parameter margins of the two full-adder cells and optimized them to obtain critical margins approaching +or-30%. Simulations of the full-adder cells have revealed critical delays and maximum clock frequencies of 58 ps and 17 GHz and 33 ps and 30 GHz, respectively.<>

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Applied Superconductivity, IEEE Transactions on  (Volume:3 ,  Issue: 1 )