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A simulation-based approach to test pattern generation for synchronous sequential circuits

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4 Author(s)
Camurati, P. ; Dipartimento di Autom. e Inf., Politecnico di Torino, Turin, Italy ; Corno, F. ; Prinetto, P. ; Reorda, M.S.

Particular design environments, e.g., those based on partial scan, may prevent design for testability techniques from reducing testing to a combinational problem: ATPG for sequential devices thus remains a challenge. Random and deterministic structure-oriented techniques are state-of-the-art, but there is a growing interest in methods that resort to the automaton of the circuit. The authors present SETA, a sequential test generator based on automata, an ATPG applicable to synchronous circuits working in the fundamental mode. SETA generates test patterns while trying to disprove the equivalence of two automata. SETA is simulation-based: within the theoretical framework of the product machine, state-of-the-art simulation techniques are used to yield satisfactory experimental results on the ISCAS89 benchmark set.<>

Published in:

VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE

Date of Conference:

7-9 April 1992