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A method for consistent fault coverage reporting

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3 Author(s)
Debany, W.H., Jr. ; Rome Lab., Griffiss Air Force Base, NY, USA ; Kwiat, K.A. ; Al-Arian, S.A.

Procedure 5012 of Mil-Std-883, which describes requirements for the logic model, the assumed fault model and universe, fault classing, fault simulation and reporting of test results for digital microcircuits is described. The procedure provides a consistent means of measuring fault coverage regardless of the specific logic and fault simulator used. Procedure 5012 addresses complex, embedded structures such as random-access memories (RAMs), read-only memories (ROMs), and programmable logic arrays (PLAs) weighting gate-level and non-gate-level structures by transistor counts to arrive at overall fault coverage.<>

Published in:

Design & Test of Computers, IEEE  (Volume:10 ,  Issue: 3 )