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High-performance dual-gate CMOS utilizing a novel self-aligned pocket implantation (SPI) technology

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4 Author(s)
Hori, A. ; Matsushita Electr. Ind. Co. Ltd., Osaka, Japan ; Segawa, M. ; Kameyama, S. ; Yasuhira, M.

A self-aligned pocket implantation (SPI) technology is discussed. This technology features a localized pocket implantation using the gate and drain electrodes (TiSi2 film) as well as self-aligned masks. The gate polysilicon is patterned by KrF excimer laser lithography. The measured minimum gate length Lg (the physical gate length) is 0.21 μm for both N- and P-MOSFETs. A newly developed photoresist was used to achieve less than quarter-micrometer patterns. This process provides high punchthrough resistance and high current driving capability even in such a short channel length. The subthreshold slope of the 0.21-μm gate length is 76 mV/dec for N-MOSFETs and 83 mV/dec for P-MOSFETs. The SPI technology maintains a low impurity concentration in the well (less than 5×10 16 cm-3). The drain junction capacitance is decreased by 36% for N-MOSFETs and by 41% for P-MOSFETs, compared to conventional LDD devices, which results in high-speed circuit operation. The delay time per stage of a 51-stage dual-gate CMOS ring oscillator is 50 ps with a supply voltage of 3.3 V and a gate length of 0.36 μm, and 40 ps with a supply voltage of 2.5 V and a gate length of 0.21 μm

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Electron Devices, IEEE Transactions on  (Volume:40 ,  Issue: 9 )