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Architecture design of a fully asynchronous VLSI chip for DSP custom applications

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2 Author(s)
X. Fan ; Sch. of Inf. Sci. & Technol., Flinders Univ., Adelaide, SA, Australia ; N. Bergmann

A fully asynchronous, distributed VLSI architecture is introduced for dedicated real-time digital signal processing applications. The architecture is based on a data-driven computing model to allow maximum exploitation of the fine-grained concurrency. An asynchronous, self-time signaling protocol is used in the architecture to naturally match data-driven computing and circumvent the clock skew problem. After a brief description of the architecture, key issues of the architecture, such as the interconnection network, data identification, and operand matching are discussed. Finally, disadvantages of the architecture and future work are outlined

Published in:

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on  (Volume:5 )

Date of Conference:

10-13 May 1992