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A performance-driven analog-to-digital converter module generator

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3 Author(s)
G. Jusuf ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; P. R. Gray ; A. L. Sangiovanni-Vincentelli

A performance-driven analog-to-digital converter (ADC) module generator, CADICS, which generates ADC netlists and layouts from a set of specifications is presented. The module generator consists of a circuit synthesis which is based on a hierarchical optimization approach and a layout synthesis which was implemented using a hierarchical layout procedure. At each level of performance, silicon area and power dissipation are optimized so that they are comparable with manual design. The synthesis is built around a one-bit-per-cycle algorithmic A/D converter architecture. Layouts of 6-b, 8-b, and 10-b ADCs generated by CADICS in a 2-μm CMOS process are shown

Published in:

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on  (Volume:5 )

Date of Conference:

10-13 May 1992