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Realization of array architectures for video compression algorithms

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4 Author(s)
Yeu-Shen Jehng ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Liang-Gee Chen ; Tzi-Dar Chiueh ; Thou-Ho Chen

A practical design technique is presented to realize an array architecture for hierarchical block matching algorithms. A mapping procedure has been applied to derive the array processor from the algorithm. The proposed systolic array is derived to reduce the input/output bandwidth and the hardware cost. This systolic array is configured to be a single-chip of a cascaded architecture to match the requirements of real-time video applications

Published in:

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on  (Volume:4 )

Date of Conference:

3-6 May 1992