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Design-for-reliability rules for hot-carrier resistant CMOS VLSI circuits

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3 Author(s)
Sun, W. ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; Leblebici, Y. ; Kang, S.M.

The authors present a macro-model for evaluating the hot-carrier-related degradation of simple CMOS circuits and the design-for-reliability rules for some CMOS circuits. The influence of various design parameters on long-term reliability is investigated using the macro-model. It is shown that, for CMOS inverter circuits, the degradation due to hot-carrier effects can be expressed as a function of (i) the ratio of nMOS transistor size over the load capacitance and (ii) the input rise time. Combining propagation delay and degradation cost functions, an optimum value of the scaling factor for inverter chains can be found which minimizes the overall delay as well as the hot-carrier-induced degradation

Published in:

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on  (Volume:3 )

Date of Conference:

10-13 May 1992