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Interconnection network switch design for parallel DSP systems

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2 Author(s)
Fujii, T. ; NTT Transmission Syst. Lab., Yokosuka, Japan ; Ono, S.

Describes the design of an interconnection network switch VLSI for parallel digital signal processing (DSP) systems. This VLSI features 6×400 Mb/s bidirectional communication ports and 1.44-Gb/s internal switching capability for realizing efficient packet-switched communication among many processing elements. To achieve this performance with existing CMOS technology, the transport line transfers 8 b in parallel at 50 MHz; input data are first multiplexed up to 64 b and switched at 25 MHz. An automatic routing function is implemented on each switch using a distributed routing table scheme. A high-level behavioral description based CAD (computer-aided design) system called PARTHENON is used to design the functions and logic circuits of this VLSI. The suitability and effectiveness of PARTHENON for switch design are also shown in terms of parallel operation and finite state machine design

Published in:

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on  (Volume:3 )

Date of Conference:

10-13 May 1992

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