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A high speed digital data separator design using real time DSP for disk drive applications

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7 Author(s)
Beomsup Kim ; Philips Res. Palo Alto, CA, USA ; Greco, J.D. ; Helman, D.N. ; Ngo, H.
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A salient digital data separator architecture using a digital phase-locked loop (PLL) based on high-speed digital filters for disk drives with constant density recording is described. In read mode this data separator performs clock recovery, data synchronizationf, sync field search and detect, address mark detect, and data decoding from (1,7) RLL (run-length-limited) to NRZ (nonreturn to zero). And in the write mode it performs write precompensation, encoding from NRZ to (1,7) RLL, and the generation of the preamble field and address mark. The fast acquisition digital PLL, based on high-speed digital filters, has several advantages over the conventional PLLs. Since locking and tracking is done in the digital domain the digital PLL can much more easily achieve zero phase start, variable gain and bandwidth control for fast acquisition and stable tracking, programmable window symmetry programming, and constant density recording on the magnetic media

Published in:

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on  (Volume:2 )

Date of Conference:

10-13 May 1992