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Using adjacent sampling for error correcting analog-to-digital converters

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3 Author(s)
Hummels, D.M. ; Dept. of Electr. & Comput. Eng., Maine Univ., Orono, ME, USA ; Irons, F.H. ; Kennedy, S.P.

The authors address the use of neighboring samples to linearize the behavior of high-speed flash analog-to-digital converters (ADCs). A novel converter architecture is proposed in which a single flash comparator bank and dual latch/encoder stages allow samples to be taken at intervals much smaller than the sampling period. The result is a calibration/compensation procedure which is less sensitive to calibration frequency than are previous schemes. Using two TRW-1025 converters to implement the architecture shows an improvement in the spurious free dynamic range of between 10 dB and 20 dB over the majority of the Nyquist band

Published in:

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on  (Volume:2 )

Date of Conference:

10-13 May 1992