Bounding the test sequence length of sequential circuits by the partial scan design

The selection of a minimal number of scan elements so that the necessary test sequence length can be kept below a given limit, thus bounding the test generation effort for the resulting sequential circuit, is addressed. The selection strategy is based on a calculus for the estimation of the maximum test sequence length, consisting of over 20 rules. Experimental results with the ISCAS-89 benchmark circuits show the efficiency of this approach.<
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