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Statistical degradation analysis of digital CMOS IC's

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3 Author(s)
Rangavajjhala, V.S. ; Cirrus Logic Inc., Milpitas, CA, USA ; Bhuva, B.L. ; Kerns, S.E.

A statistical switch-level simulator, based on interval and statistical analysis techniques, that simulates the effects of fabrication process fluctuations and environmental effects on digital CMOS integrated circuits is presented. The simulator is computationally very cost-effective compared to conventional Monte Carlo simulators, yet produces results with equal accuracy. The simulator enables analysis of the sensitivity of critical function and performance levels to a variety of parameter variations, thus providing a basis for establishing correspondence between process control, yield, and reliability

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:12 ,  Issue: 6 )

Date of Publication:

Jun 1993

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