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Intractability in linear switch-level simulation

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2 Author(s)
Huang, L.P. ; Carnegie Mellon Univ., Pittsburgh, PA, USA ; Bryant, R.E.

The linear switch-level model represents a MOS transistor as a voltage-controlled linear resistor and a storage node as a grounded, linear capacitor. For logic simulation, the linear switch-level model offers an attractive tradeoff between resolution/accuracy and computational complexity over gate-level and circuit-level models. However, analysis of MOS networks using the linear switch-level model becomes increasingly difficult in the presence of unknown values, and heuristic methods are often employed. It is shown that the complexity of computing maximum and minimum steady-state voltages of a general MOS network using the linear switch-level model in the presence of unknown values is NP-complete. These results partially justify the use of heuristic methods when unknown values are present

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:12 ,  Issue: 6 )