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70-MHz 2-μm CMOS bit-level systolic array median filter

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3 Author(s)
R. Roncella ; Dipartimento di Ingegneria dell'Inf. Elettronica, Pisa Univ., Italy ; R. Saletti ; P. Terreni

An algorithm for VLSI median filtering of one-dimensional signals of complexity linearly dependent on the filter window length is described. The algorithm is implemented as a bit-level systolic array (BLSA), in order to achieve high performance. A single-chip median filter characterized by a window length of 25 8-b samples, and by operation on three interleaved independent sequences for a total of 75 samples, is presented as a demonstration of the concept. The throughput relevant to one sequence is 1/3 for this chip, whereas the theoretical maximum allowed by the algorithm is 1/2. Prototypes designed with a 2-μm CMOS technology have been successfully tested at a clock frequency over 70 MHz

Published in:

IEEE Journal of Solid-State Circuits  (Volume:28 ,  Issue: 5 )