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A high-precision VLSI winner-take-all circuit for self-organizing neural networks

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2 Author(s)
Joongho Choi ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; Sheu, B.J.

The design and implementation of a high-precision VLSI winner-take-all (WTA) circuit that can be arranged to process 1024 inputs are presented. The cascade configuration can be used to significantly increase the competition resolution and maintain high-speed operation for a large-scale network. The total bias current increases in proportion to the number of circuit cells so that a nearly constant response time is achieved. A unique dynamic current steering method is used to ensure that only a single winner exits in the final output. Experimental results for a prototype chip fabricated in a 2-μm CMOS technology show that a cell can be a winner if its input is larger than those of the other cells by 15 mV. The measured response time is around 50 ns at a 1-pF load capacitance. This analog winner-take-all circuit is a key module in the competitive layer of self-organizing neural networks

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:28 ,  Issue: 5 )