Cart (Loading....) | Create Account
Close category search window
 

A bipolar 1.5 Gb/s monolithic phase-locked loop for clock and data extraction

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Wu, J.-T. ; Hewlett-Packard Co., San Jose, CA, USA ; Walker, R.C.

The design of a monolithic phase-locked loop (PLL) used in a gigabit serial data link interface for clock and data extraction is described. Implemented in a triple-metal 25-GHz f/sub t/ bipolar process and consuming 85 mA from a 5 V-supply, the PLL has a wide frequency acquisition range, from 600 MHz to 1.5 GHz, and a recovered clock phase jitter of less than 18.3 ps r.m.s. The PLL requires only one external component (the loop filter capacitor) needs no adjustment, and is suitable for large-scale integration.<>

Published in:

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Date of Conference:

4-6 June 1992

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.