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A 100 MHz superscalar PA-RISC CPU/coprocessor chip

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4 Author(s)
Yetter, J. ; Hewlett-Packard Co., Fort Collins, CO, USA ; Miller, B. ; Jaffe, W. ; Delano, E.

A RISC CPU chip has been designed for 100-MHz operation. The chip combines a 32-b integer core and a full 64-b floating point coprocessor on a 1.43-cm*1.43-cm die. The chip is fabricated in a 0.8- mu m CMOS process with three layers of aluminum interconnect. It contains in excess of 850000 transistors. Many of the CPU circuits were adapted from an earlier CPU designed for 66 MHz in a 1- mu m-gate process. Careful characterization of that circuit combined with design shrinkage to 0.8 mu m yielded the desired performance. Other circuits were directly designed for 100-MHz operating frequency in the scaled process.<>

Published in:

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Date of Conference:

4-6 June 1992