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A 66-MHz configurable secondary cache controller with primary cache copyback support

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13 Author(s)
Reed, P. ; Motorola Microprocessor Group, Austin, TX, USA ; Alexander, M. ; Beavers, B. ; Evers, R.
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The authors describe a 66-MHz secondary cache controller which supports a primary cache operating in copyback mode. The device integrates a 278-kb direct-mapped cache tag array plus control logic to provide full multiprocessing capability and is configurable to support cache sizes from 256 kbytes to 1 Mbyte. Implemented in a 0.8- mu m twin-well double-poly triple-metal CMOS process, the device uses a high-resistivity poly load memory cell to achieve high density.<>

Published in:

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Date of Conference:

4-6 June 1992

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