By Topic

A neural network embedded processor with a dynamically reconfigurable pipeline architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Satonaka, T. ; Matsushita Electron. Corp., Osaka, Japan ; Tamura, Y. ; Morishita, T. ; Inoue, A.
more authors

A neural network embedded processor with a dynamically reconfigurable pipeline architecture is described. The processor dynamically changes connections between arithmetic units and memories to obtain the optimum pipeline configuration at every step of the network calculation. The processor attains a learning speed of 18 million connection updates per second (MCUPS), which is approximately 20 times that of the conventional digital signal processor. This processor provides expansibility in the calculation through a larger multilayer network by means of a network decomposition and a distributed processing approach.<>

Published in:

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Date of Conference:

4-6 June 1992