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A neural network embedded processor with a dynamically reconfigurable pipeline architecture

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7 Author(s)
Satonaka, T. ; Matsushita Electron. Corp., Osaka, Japan ; Tamura, Y. ; Morishita, T. ; Inoue, A.
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A neural network embedded processor with a dynamically reconfigurable pipeline architecture is described. The processor dynamically changes connections between arithmetic units and memories to obtain the optimum pipeline configuration at every step of the network calculation. The processor attains a learning speed of 18 million connection updates per second (MCUPS), which is approximately 20 times that of the conventional digital signal processor. This processor provides expansibility in the calculation through a larger multilayer network by means of a network decomposition and a distributed processing approach.<>

Published in:

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Date of Conference:

4-6 June 1992

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