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A quick intelligent program architecture for 3 V-only NAND-EEPROMs

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7 Author(s)
Tanaka, T. ; Toshiba Corp., Kawasaki, Japan ; Tanaka, Y. ; Nakamura, H. ; Oodaira, H.
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A quick program/program verify architecture with an intelligent verify circuit for 3-V-only NAND-EEPROMs is described. The verify circuit, which is composed of two transistors, provides a simple, intelligent program algorithm for 3-V-only operation. The total programming time is reduced to 50%. By using intelligent verify circuits, the memory cells which require more time to reach the program state are automatically detected. Verify-read, the modification of program data, and data reload are performed simultaneously. The chip size penalty is estimated to be only 1% for a 16-Mb NAND-EEPROM.<>

Published in:

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Date of Conference:

4-6 June 1992

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