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A new decoding scheme and erase sequence for 5 V only sector erasable flash memory

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7 Author(s)
Nakayama, T. ; Mitsubishi Electr. Corp., Itami, Japan ; Kobayashi, S. ; Miyawaki, Y. ; Futatsuya, T.
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The authors describe a decoding scheme and erase sequence for a 5-V-only sector-erasable flash memory. A source line decoder eliminates the erase disturb problem and lowers the power consumption. The maximum switching voltage is reduced to 10 V, which makes possible a tight word line pitch for a 64-Mb flash memory. Narrow threshold voltage distribution of erased memory cells is obtained by programming after erase.<>

Published in:

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Date of Conference:

4-6 June 1992