A 333 MHz, 72 Kb BiCMOS pipelined buffer memory with built-in self test

The designs for a high-speed BiCMOS buffer memory and a high-speed BIST circuit are studied. A BiCMOS pipelined read architecture constructed using a latched ECL sense amplifier and a clocked ECL-CMOS level converter is proposed, and a BiCMOS complimentary clocked driver technique is described. The memory is constructed with 0.8- mu m technology and achieves 333-MHz operating frequency in simulation. It is confirmed that the BIST circuit, using linear feedback shift registers (LFSRs), can examine the memory at maximum operating frequency without degradation in the speed performance of the memory.<
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