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Clocking strategies in high performance processors

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1 Author(s)
M. Horowitz ; Stanford Univ., CA, USA

Recent improvements in processor implementation have focused attention on clock generation and distribution. The clocks and the latches connected to them must be carefully engineered to meet the performance requirements of the system. The author reports on the difficulty encountered in generating clocks for current processors, and describes techniques used to create these clocks, including minimizing both the internal clock skew and the skew between the internal logic and the external world. On-chip clock distribution, zero delay buffers, and self-timed systems are discussed.<>

Published in:

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Date of Conference:

4-6 June 1992