Cart (Loading....) | Create Account
Close category search window
 

Synthesis on multiplexer-based programmable devices using (ordered) binary decision diagrams

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Besson, T. ; Inst. Nat. Polytech. de Grenoble, France ; Bouzouzou, H. ; Crastes, M. ; Soucier, G.

Presents synthesis techniques on the Actel multiplexer-based programmable gate arrays. The internal structure of these devices is exploited through binary decision diagrams based algorithms. According to the speed/area trade-off, either classical or reduced ordered Binary Decision Diagrams are used. Emphasis is put on the determination of a good ordering for the ROBDD construction. Results on a large set of international benchmarks and comparisons with existing work are provided

Published in:

Euro ASIC '92, Proceedings.

Date of Conference:

1-5 Jun 1992

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.